1. The Field of the Invention
The present invention relates to methods of forming a conductive structure over a charge conducting region. More particularly, the present invention relates to methods of forming a vertically oriented structure composed of conductive material projecting from a charge conducting region. The method of the present invention is particularly useful for forming a capacitor storage node between two gate stacks situated on a semiconductor substrate.
2. The Relevant Technology
Integrated circuits provide the logic and memory of computers and other intelligent electronic products. Electronic "chips" on which the integrated circuits are situated have advanced in capability to a level that has made the computers and other intelligent electronic devices highly functional. Integrated circuits are also being manufactured economically allowing the highly functional computers and other intelligent electronic products to be provided to consumers at an affordable cost.
Integrated circuits are currently manufactured by an elaborate process in which semiconductor devices, insulating films, and patterned conducting films are sequentially constructed in a predetermined arrangement on a semiconductor substrate. In the context of this document, the term "semiconductor substrate" is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term "substrate" refers to any supporting structure including but not limited to the semiconductor substrates described above.
Conventional semiconductor devices which are formed on a semiconductor substrate include capacitors, resistors, transistors, diodes, and the like. In advanced manufacturing of integrated circuits, hundreds of thousands of these semiconductor devices are formed on a single semiconductor substrate.
The computer and electronics industry is constantly under market demand to increase the speed at which integrated circuits operate, to increase the capabilities of integrated circuits, and to reduce the cost of integrated circuits. One manner of accomplishing this task is to increase the density with which the semiconductor devices can be formed on a given surface area of a single semiconductor substrate. In so doing, the semiconductor devices must be decreased in dimension in a process known as miniaturization. In order to meet market demands and further the miniaturization of integrated circuits, the processes by which the semiconductor devices are formed are in need of improvement. The challenge in miniaturizing integrated circuits is to do so without greatly increasing the cost of the processes by which integrated circuits are manufactured. Accordingly, the new processes must also be relatively simple and cost effective.
One structure which is frequently formed in integrated circuit manufacturing and for which improved methods of formation are needed is the capacitor. The capacitor is formed with a storage node, a cell plate, and a dielectric layer therebetween. The storage node and the cell plate are typically patterned out of polysilicon by conventional photolithography and dry etching. The dielectric layer is formed in an intervening process between the formation of the storage node and the cell plate, typically by growth of silicon dioxide through exposure of the polysilicon of the storage node to oxygen at an elevated temperature.
An important consideration in forming capacitors in integrated circuits is surface area. A large surface area of the storage node and cell plate is necessary in order to provide high capacitance and therefore optimal performance of the capacitor. Balanced against this need is the competing requirement that the capacitor also occupy a minimum of space on the semiconductor substrate on which the capacitor is formed. One manner in which the semiconductor industry has approached minimal space capacitor formation is to form the capacitor at a significant distance above the semiconductor substrate.
A typical arrangement of the basic structure used in the formation of a memory cell is a silicon substrate with a plurality of source/drain regions therein, where a pair of gate stacks are situated on the silicon substrate, the pair of gate stacks having a capacitor therebetween. Miniaturization demands require that the gate stacks be closely spaced together.
Typically in the formation of a capacitor, a storage node is formed above a source/drain region and projects upwards therefrom. To form the storage node, a layer of insulating material, such as borophosphosilicate glass (BPSG), is formed over the gate stacks and the source/drain region therebetween. A polysilicon layer deposited over the insulating layer is patterned and etched to form trenches in the insulating layer. A spacer comprising polysilicon is formed by a spacer etch in the trench to narrow the trench to the necessary size. After the spacer etch and a subsequent contact etch, the trenches extend to the silicon substrate.
Usually, a layer of doped polysilicon is formed over the exposed structures and within the trenches. A chemical mechanical planarization (CMP) process planarizes the insulating layer which results in an electrically insulated conductive structure which is used to form a storage node for a capacitor. A dielectric layer and a cell plate are formed over the storage node to complete a capacitor structure.
Current processing to form the capacitor described above requires multiple depositions. What is needed is a capacitor structure that can be formed with a minimized number of depositions so as to reduce both cost and throughput time. A reduction in the masks required is also desired. It is desirable to reduce the number of separate process steps, thereby increasing the through put rate.